The inventors have observed that interfacial engineering (e.g., removing contaminants, modifying surface morphology, restructuring lattices, or the like) is advantageous for sub-10 nm node devices. Many key processes, such as epitaxial film growth, metallization, etc., rely on the quality of the interface to enhance device performance. To make a high quality interface, not only are chemical reactions necessary to clean the surface, but also some physical treatment like physically displacing the lattice to smooth the surface are critical to device fabrication. For example, surface oxidation always occurs on silicon during air exposure, and highly selective native oxide removal is desired to minimize silicon loss. However, the interface is typically a mixture of many elements such as carbon, nitrogen, and the like, and is often rough.
The inventors have further observed that a pure oxide removal process is not sufficient to improve the interface quality. For example, a remote NH3/NF3 plasma provides highly selective SiO2/Si removal by forming NH4F which is easy to react with Si—O bonds at room temperature, but not with Si—Si bonds. The polymer NH4F—SiO2 can be sublimated when sufficiently heated. However, because NH4F only sticks to Si—O, when the interface is silicon rich, it takes a long time to remove oxygen from surface, and the NH4F would also remove substantial amounts of true silicon oxide which has 1:2 Si to O ratio. This is problematic because an SiO2 liner is often utilized to protect the transistor, and if this protective dielectric film is removed, the device can be shorted and yield will drop. Also, in remote plasma processes, many ions are not able to survive to reach the substrate, and so the energy flux incident on the substrate surface is very small, making it extremely difficult to modify the surface morphology with a remote plasma. Furthermore, the remote plasma removal is typically isotropic and strongly dependent on the geometric receiving angle of reactants. For example, more oxide removal is expected at the feature top than at the bottom due to the limited species delivery to the feature bottom. This problem is exacerbated when the feature is tiny, for example in sub-10 nm node devices.
Thus, the inventors have provided improved methods for surface interface engineering in semiconductor fabrication.